Syllabus of Andhra University BTech Computer Science Engineering - CSE 4.1.5 - Fault Tolerant Computing (Elective I)

Fourth year - First Semester

Instruction: 3 Periods & 1 Tut /week
Univ. Exam : 3 Hours

Sessional Marks: 30
Univ-Exam-Marks:70

Basic Concepts of Reliability
Faults in Digital Circuits
Test Generation

Introduction to Fault Tolerant Design of Digital Systems: Fault Tolerance, Static redundancy, Dynamic redundancy, Fault tolerant design of Memory systems, Practical Fault Tolerant Systems: FTMP, ESS, COMTRAC

Introduction to Self-Checking Logic: The two rail Checker,
Design for Testability: Testability, Controllability and Observability, Design of testable Combinational Logic Circuits, Testable design of Sequential Circuits, The scan path technique, Designing testability into logic boards

Text Books:

Fault Tolerant and Fault Testable Hardware Design, Parag K. Lala, PHI, 1985

Reference:

1. Fault Tolerant Computing Theory and Techniques-Volume I, D.K. Pradhan, PHI, 1986

2. Testing of Digital Systems, Niraj jha and Sandeep Gupta, Cambridge University Press, 2003