Syllabus of Andhra University BTech Information Technology - IT 4.2.3 - VHDL (Elective II)

Fourth year - Second Semester

Instruction: 3 Periods & 1 Tut /week
Univ. Exam : 3 Hours

Sessional Marks: 30
Univ-Exam-Marks:70

1. Overview of Digital Design with Vermilion HDL

2. Hierarchical Modeling Concepts

3. Basic Concepts

4. Modules and ports

5. Gate-Level Modeling

6. Dataflow Modeling

7. Behaviour Modeling

8. Tasks and Functions

Text Book:

1. Verilog HDL – A Guide to Digital Design and Synthesis, Samir Palnitkar, Pearson Education Pte. Ltd. (chapters: 1,2,3,4,5,6,7,8), 2001

Reference Books:

1. Fundamentals of Digital Logic with Verilog Design, Stephen Brown and Zvonko Vranesic, Tata - McgrawHill, 2002

2. A Verilog HDL Primer, J. Bhasker, Second Edition, Star galaxy Pub., 1999