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Home / Testpapers / Jawaharlal Nehru Technological University / Under Graduate Courses /
NR 310201 - Computer Organization
Set 3 - November 2003 |
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Code No-NR- 310201
III-B.Tech. I-Semester Supplementary Examinations, November-2003
COMPUTER ORGANIZATION
Set No. 3
(common to EEE, ECE, EIE and ET)
Time: 3 Hours
Max. Marks: 80
Answer any FIVE questions
All questions carry equal marks
1. (a) Give the functional organization of a digital computer and explain the function of each element of a computer.
(b) Describe with suitable illustrations the partial program execution on showing the relevant portions of memory and CPU registers, to perform addition of contents of two memory locations.
2. (a) Compare the addressing model of Pentium and power PC control transfer operation types.
(b) What are the different data transfer instructions ?
3. Define the term addressing mode. Also explain the different addressing modes available in 8085 with an example for each.
4. (a) With the help of a diagram, clearly explain the functioning of a microprogrammed controkl unit.
(b) Microprogrammed unit is slower than hardwired unit. Justify this statement.
5. (a) Differentiate among different semiconductor memories.
(b) Describe set associative mapping technique of cache memory.
6. (a) What do you mean by page fault ?
(b) Explain how number of page faults can be calculated for the given page trace using FIFO page replacement strategy ?
(Assume 3 frames are available in the memory).
7. (a) What is the necessity of I/O modules? Explain.
(b) What type of commands an I/O interface may receive? Explain.
8.(a) Describe the organization of DMA.
(b) How are priority interrupt implemented ? Explain.
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