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Home / Testpapers / Jawaharlal Nehru Technological University / Under Graduate Courses /
NR 310201 - Computer Organization
Set 4 - November 2003 |
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Code No-NR- 310201
III-B.Tech. I-Semester Supplementary Examinations, November-2003
COMPUTER ORGANIZATION
Set No. 4
(common to EEE, ECE, EIE and ET)
Time: 3 Hours
Max. Marks: 80
Answer any FIVE questions
All questions carry equal marks
1. (a) Describe an instruction execution using a state diagram.
(b) Describe a program flow of control without and with interrupts.
2. (a) Compare the addressing modes of Pentium and Power PC processors.
(b) Explain the Pentium instruction formates.
3. (a) Write and explain the timing diagram for Memory Read and I/O Write cycles with neat diagrams.
(b) Write a program for 8085 microprocessor to transfer a block of N data bytes to next N consecutive locations. Value of N is known.
4. (a) What is a micro operation? With the help of a diagram explain the constituent elements of a program execution.
(b) Expand and explain the following terms:
MAR, MBR, PC, IR.
5. What are the different mapping techniques of cache memory? Describe each techniques with suitable diagram.
6. (a) What do you mean by thrashing?
(b) Explain how number of page faults can be calculated for the given page trace using LRU page removal techniques.
(Assume 4 frames are available in the memory).
7. (a) What is the purpose of I/O interface? Explain. Give the Communication link between the processors I/O BUS and several peripherals.
(b) Describe different commands that an I/O with face receive from CPU.
8. Why are read and write control lines in a DMA Controller bi-directional ? Under what condition and for what purpose are they used as inputs ? Under what condition and for what purpose are they used as outputs ? Explain.
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