Test Papers / Previous Question Papers of IGNOU CS12 Computer Architecture December 2002

ADCA / MCA (III Yr)
Term-End Examination

December, 2002

CS12 : Computer Architecture

Time: 3 hours
Maximum Marks: 75

1(i) The SPARC architecture can be implemented with two to eight register windows for a total of 40 to 130 GPRs (General Purpose Registers) in the integer unit. Explain how the GPRs are organized into overlapping windows in each of the following designs: [10]

(a) Use 10 GPRs to construct two windows.
(b) Use 72 registers (GPRs) to construct four windows.
(c) In what sense is the SPARC considered a scalable architecture?
(d) Explain how to use the overlapped windows for parameter passing between the calling procedure and the called procedure.

(ii) Answer the following question: [20]

(a) Comment on the advantages in using SIMD computers as compared with the use of pipelined supercomputers for vector processing.

(b) Describe the language features of parallelism.

(c) Describe the basic metrics affecting the scalability of a computer system for a given application.

(d) Make diagrams of mesh and torus interconnection network and describe its characteristics.

2. Explain the following terms: [15]

(a) Write through vs Write back caches

(b) Detection of parallelism using Bernstein's condition

(c) Low order memory interleaving

(d) Inverted page table

(e) Tomasulo's algorithm for scheduling instruction through an instruction pipeline.

3. Differentiate among the following: [15]

(a) High-end mainframes and Near supercomputers

(b) Tightly coupled and Loosely coupled system

(c) Superscalar and VLIW (Very Large Instruction Word) architectures in terms of H/W and S/W requirements

(d) Data flow computers and Reduction computers

(e) Buffer deadlock vs. Channel deadlock

4. Answer the following questions on designing scalar RISC or super scalar RISC processors: [15]

(i) Why do most RISC integer units use 32 general purpose registers?

(ii) What are the design tradeoffs between a large register file and a large D-cache?

(iii) Explain the relationship between the integer unit and floating point unit in most RISC processors with scalar or superscalar organizations.

5. Answer the following questions: [15]

(i) Why is synchronous pipeline selected over asynchronous pipeline?

(ii) Design a four way sector mapping cache organization and explain its functioning.

(iii) What are the limitations of conventional UNIX for parallel processing?

6. Discuss the following: [15]

(a) What is multivector computing? How is it useful for supercomputer?

(b) Comment on synchronization and communication features needed in parallel programming languages.

(c) What is meant by Cache-only Memory Architecture (COMA) model? How is it different from non-uniform memory access model?