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ADCA / MCA (III Yr)
Term-End Examination
December, 2005
CS12 : Computer Architecture
Time: 3 hours
Maximum Marks: 75
1. (a) Analyze the data dependence among the following statements in a given program fragment :
LOAD R1, M(100)
LOAD R2, M(104)
MULTI R1 R2
INC R1
STORE M(110), R1
where Memory (100) contains 66 initially and Memory (104) contains 6 initially. (5)
(b) Describe the Daisy chained bus arbitration scheme in a multiprocessor system through an appropriate diagram. Explain its advantages and its shortcomings. (5)
(c) Explain any three features of Data parallelism and Process management of parallel programming languages. (6)
(d) Consider a Cache (M1) and Memory (M2) hierarchy with the following characteristics:
M1 :16 K words
M2 : 1 M words
Assume eight-word cache blocks and a set size of 256 words with set-associative mapping. Show the
mapping between M2 and M1. (5)
(e) Differentiate between VLIW and Superscalar machines. Also show the pipeline operation of VLIW processor through an appropriate diagram. (4)
(f) Explain the following terms :
(i) Buffer deadlock vs. Channel deadlock
(ii) Unicast vs. Multicast
2. Characterize the architectural operations of SIMD and MIMD computers. Distinguish between multiprocessors and multicomputers based on their structures, resource sharing and interprocessor communications. Also, explain the differences among UMA, NUMA, COMA and NORMA Computers.
3. (a) A two level memory system has eight virtual pages on a disk to be mapped into four-page frames in the main memory. Page trace is given as
1, 0, 2, 2, 1, 7, 6,7, 0, 1, 2, 0, 3, 4
Using the FIFO page replacement policy, compute the hit ratio in the main memory. Show the successive virtual pages residing in the four frames. (6)
(b) Differentiate between Dataflow, and Reduction Computers in terms of advantages and disadvantages. (4)
(c) Explain any two differences between Static and Dynamic interconnection networks. (5)
4. Define the following using appropriate formulae :
(a) CPI (2)
(b) MIPS rate
(c) Throughput rate
(d) Speed-up factor of K-stage pipelining over an equivalent non-pipelining procesor (3)
(e) Pipeline performance/cost ratio
(f) Efficiency and throughput of linear K-stage pipeline (3)
5. (a) Distinguish between Static dataflow computers and Dynamic dataflow computers. (4)
(b) Consider the forward Loopcarried dependence (LCD) in the following loop :
Do I = 1, N
A(I) = A (I+1) + 3.14159
Enddo
Explain why a forward LCD does not prevent vectorization of a loop. (3)
(c) Distinguish between Spin locks and Suspend locks for sole access to a critical section. (4)
(d) Explain two differences between Coarse grain and Medium grain level parallelism. (4)
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