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CS12 Computer Architecture June 1998
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Test Papers / Previous Question Papers of IGNOU CS12 Computer Architecture June 1998

ADCA / MCA (III Yr)
Term-End Examination

June, 1998

CS12 : Computer Architecture

Time: 3 hours
Maximum Marks: 75

Note : Question No. 1 is compulsory. Answer any three questions from the rest.

1. (a) What is superpipelining? How is it different from Superscalar pipeline?

(b) Analyse the data dependence of the statements of the following program:
S1: Load RA, M[20] /RA ¬ M[20] /
S2: Load RB, M[25] /RB ¬ M[25] /
S3: Sub RA, RB /RA ¬ RA- RB /
S4: Mult RA, 5 /RA ¬ RA * 5 /
S5: STORE M[20], RA /M[20] ¬ RA /

Draw the dependence graph for the dependencies.

(c) What are the limitations of conventional UNIX for parallel processing systems?

(d) Compare and contrast the cache Associative and sector caches.

(e) Discuss the architecture environment for a Multi-threaded computer model.

(f) What is m-way memory interleaving? Discuss the c-access memory scheme.

2. Discuss the following terms in the context of computer architecture:
(a) Systolic arrays
(b) Multiprocessing requirements at processor level
(c) Scalability
(d) Cross bar switch
(e) VLIW architecture

3.(a) What are the differences between static and dynamic dataflow Computers?

(b) Compare and contrast the central and distributed bus arbitration schemes.

(c) What is multivector computing? How is it useful for supercomputers?

4. (a) What are the different types of vector instructions? Discuss.

(b) What is meant by Cache-Only Memory Architecture (COMA) model? How is it different from non-uniform-memory-access model?

(c) What is meant by hierarchical bus system for multiprocessing systems?

5. Write short notes on the following in the context of computer architecture:

(i) Multifunctional pipelines
(ii) Monitors
(iii) Multicomputers
(iv) Clock rate, MIPS rate and throughput
(v) Branch handling in instruction pipeline

6. Discuss the following in the context of parallel languages and compilers:
(i) Parallel code generation
(ii) Parallel flow control
(iii) Parallel arrays
(iv) Synchronization and communication features needed in parallel languages
(v) Process management features needed for parallel languages

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