Test Papers / Previous Question Papers of IGNOU CS12 Computer Architecture December 2005

ADCA / MCA (III Yr)
Term-End Examination

December, 2005

CS12 (S): Computer Architecture

Time: 3 hours
Maximum Marks: 75

1. (a) Explain any three differences between memory to memory architecture and register to register architecture in vector pipelining. (6)

(b) Derive, with respect to super-pipelined design, the speedup factor over the base machine, and explain each stage. (5)

(c) Define five levels of parallelism in program execution on modern computer. (5)

(d) Explain the effective access time of memory hierarchy using the access frequencies. (4)

(e) Draw two NOMA models based on a hierarchical cluster approach and shared local memory. Also list the key differences between the two. (5)

(f) With the help of diagrams, explain deadlock situation caused by a circular bit at buffers or at communication channel. (5)

2. (a) Explain the inclusion property and memory coherence requirements in a multilevel memory hierarchy. Distinguish between write through and write-back policies in maintaining the coherence in adjacent levels. (9)

(b) Computer system has a 128 byte cache. lt uses 4-bit set associative mapping with 8 bytes in each clock. The physical address size is 32-bits and the smallest addressable unit is 1 byte: Draw a diagram showing the organization of cache and indicating how physical addresses are related to cache addresses. (6)

3. Differentiate between the following: (15)
(i) Mesh versus Torus
(ii) Crossbar versus Multistage switch
(iii) Virtual channel versus Physical channel
(iv) Buffer deadlock versus Channel deadlock
(v) Asynchronous message passing vs Synchronous message passlng

4. (a) Why do most RISC integer units use 32 general-purpose registers ? Explain the concept of register windows implemented in the SPARC architecture. (5)

(b) Distinguish between Binary tree and Fat tree interconnection architecture. (5)

(c) Explain the support for data path MMU and TLB for common and separate cache architecture. (5)

5. (a) Consider a Cache (M₁) and Memory (M₂) hierarchy with the following characteristics :
M₁ : 16 K words, 35 ns access time.
M₂ : 1 M words, 250 ns access time.
Assume eight-word cache blocks and a set size of 256 words with set associative mapping.
(i) Show the mapping between M₂ and M₁.
(ii) Calculate the effective memory access time with a cache hit ratio of h = 0.90. (10)

(b) Explain the following terms associated with fast and efficient synchronization schemes on a shared memory multiprocessor :
Server synchronization and the corresponding synchronization environment. (5)