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University of Madras (UoM)

University of Madras (UoM)

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Digital Logic Fundamentals
OCTOBER 2003
U/IC 14672/NCJ

Time: Three hours
Maximum: 100 marks

PART A - (5 x 8 = 40 marks)

Answer any FIVE questions.
All questions carry equal marks.

1. Convert the following numbers as directed.
(a) (345.625)10 into its binary equivalent
(b) (FED)16 into its decimal equivalent.

2. Reduce the following Boolean expressions into its minimal form:

(a) W(K,L,M)=KL+LM+KM
(b) Z(A,B,C,D,E,F)=A +AB +ABC+ABCD + ABCDE + ABCDEF.

3. Write the truth table of an OR gate and explain its behaviour. Realise an OR gate using NAND gates only.

4. Draw the circuit using gates of an SR flip flop and obtain its truth table.

5. Draw the circuit of a radix-8 synchronous up counter and using timing diagrams explain its working.

6. Sketch the circuit of a half subtractor. Show how a full subtractor is built using half subtractors.

7. Draw the gate 4 1 it of a 1 to 4 de-multip and explain its working

8. State and explain the functions of the different logical components of an ALU.

PART B - (3 x 20=60 marks)
Answer any THREE questions.
All questions carry equal marks.

9. Describe in detail error detecting and error correcting codes. Bring out their advantages and disadvantages as error detectors.

10. A combination circuit gives an output 1 if there are exactly two ones in the input. Using a Karnaugh map design the circuit.

11. Design a counter to count the sequence 000, 001, 011, 111, 110, 100, 000....

12. Using a suitable multiplexer design a circuit to give

X (A, B, C, D) = Y- 0, 2, 3, 5, 7, 8, 9, 12,15.

13. What is a status register? What are its uses? How is a status register designed?
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